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期刊名：Ieee transactions on very large scale integration (vlsi) systems

缩写：IEEE T VLSI SYST

ISSN：1063-8210

e-ISSN：1557-9999

IF/分区：3.2/Q2

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共收录本刊相关文章索引1430条
Clinical Trial Case Reports Meta-Analysis RCT Review Systematic Review
Classical Article Case Reports Clinical Study Clinical Trial Clinical Trial Protocol Comment Comparative Study Editorial Guideline Letter Meta-Analysis Multicenter Study Observational Study Randomized Controlled Trial Review Systematic Review
Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG [0.03%]
Chung-Yi Li; Yuan-Ho Chen; Tsin-Yuan Chang; Lih-Yuan Deng; Kiwing To Chung-Yi Li; Yuan-Ho Chen; Tsin-Yuan Chang; Lih-Yuan Deng; Kiwing To
Ieee transactions on very large scale integration (vlsi) systems. 2012;20(2):385-389. DOI:10.1109/tvlsi.2010.2103332 2012
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation [0.03%]
Raychowdhury, A.; Paul, B.C.; Bhunia et al. Raychowdhury et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2005;13(11):1213-1224. DOI:10.1109/TVLSI.2005.859590 2005
Extraction of VLSI Multiconductor Transmission Line Parameters by Complementarity [0.03%]
Specogna, Ruben Specogna
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(1):146-154. DOI:10.1109/TVLSI.2012.2232320 2014
Embedded Transition Inversion Coding With Low Switching Activity for Serial Links [0.03%]
Chiu, Ching-Te; Huang, Wen-Chih; Lin et al. Chiu et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013;21(10):1797-1810. DOI:10.1109/TVLSI.2012.2219888 2013
A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With $4\times$ Oversampling [0.03%]
Lin, Jung-Mao; Yang, Ching-Yuan; Wu et al. Lin et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2015;23(4):791-795. DOI:10.1109/TVLSI.2014.2316553 2015
High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology [0.03%]
Ching-Che Chung, ; Duo Sheng, ; Sung-En Shen et al. Ching-Che Chung et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(5):1096-1105. DOI:10.1109/TVLSI.2013.2260186 2014
Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over ${\rm GF}(2^{m})$ [0.03%]
Mozaffari-Kermani, Mehran; Azarderakhsh, Reza; Chiou-Yng Lee et al. Mozaffari-Kermani et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(5):995-1003. DOI:10.1109/TVLSI.2013.2260570 2014
Intrinsic MOSFET parameter fluctuations due to random dopant placement [0.03%]
Xinghai Tang, ; De, V.K.; Meindl et al. Xinghai Tang et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1997;5(4):369-376. DOI:10.1109/92.645063 1997
Variable-Latency Floating-Point Multipliers for Low-Power Applications [0.03%]
Shiann-Rong Kuang; Jiun-Ping Wang; Hua-Yi Hong Shiann-Rong Kuang; Jiun-Ping Wang; Hua-Yi Hong
Ieee transactions on very large scale integration (vlsi) systems. 2010;18(10):1493-1497. DOI:10.1109/tvlsi.2009.2025167 2010
A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design [0.03%]
Joshi, R.V.; Kanj, R.; Ramadurai et al. Joshi et al.
Ieee transactions on very large scale integration (vlsi) systems. 2011;19(5):869-882. DOI:10.1109/tvlsi.2010.2042086 2011