IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2015;23(4):791-795. doi: 10.1109/TVLSI.2014.2316553 Q23.22025

A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With $4\times$ Oversampling

DOI: 10.1109/TVLSI.2014.2316553

摘要 查看摘要

Copyright © IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 中文内容为AI机器翻译，仅供参考！