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期刊名：Ieee transactions on very large scale integration (vlsi) systems

缩写：IEEE T VLSI SYST

ISSN：1063-8210

e-ISSN：1557-9999

IF/分区：3.2/Q2

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共收录本刊相关文章索引1430条
Clinical Trial Case Reports Meta-Analysis RCT Review Systematic Review
Classical Article Case Reports Clinical Study Clinical Trial Clinical Trial Protocol Comment Comparative Study Editorial Guideline Letter Meta-Analysis Multicenter Study Observational Study Randomized Controlled Trial Review Systematic Review
MASTER: A Multicore Cache Energy-Saving Technique Using Dynamic Cache Reconfiguration [0.03%]
Mittal, Sparsh; Cao, Yanan; Zhang et al. Mittal et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(8):1653-1665. DOI:10.1109/TVLSI.2013.2278289 2014
2.5-dimensional VLSI system integration [0.03%]
Yangdong Deng, ; Maly, W.P. Yangdong Deng
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2005;13(6):668-677. DOI:10.1109/TVLSI.2005.848814 2005
A Unified Graphics and Vision Processor With a 0.89 /spl mu/W/fps Pose Estimation Engine for Augmented Reality [0.03%]
Jae-Sung Yoon, ; Jeong-Hyun Kim, ; Hyo-Eun Kim et al. Jae-Sung Yoon et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013;21(2):206-216. DOI:10.1109/TVLSI.2012.2186157 2013
Portable, Flexible, and Scalable Soft Vector Processors [0.03%]
Yiannacouras, P.; Steffan, J. G.; Rose et al. Yiannacouras et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2012;20(8):1429-1442. DOI:10.1109/TVLSI.2011.2160463 2012
Security-Enabled Near-Field Communication Tag With Flexible Architecture Supporting Asymmetric Cryptography [0.03%]
Plos, Thomas; Hutter, Michael; Feldhofer et al. Plos et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013;21(11):1965-1974. DOI:10.1109/TVLSI.2012.2227849 2013
From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding [0.03%]
Muller, O.; Baghdadi, A.; Jezequel et al. Muller et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2009;17(1):92-102. DOI:10.1109/TVLSI.2008.2003164 2009
UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors [0.03%]
Xiaowen Wu, ; Yaoyao Ye, ; Jiang Xu et al. Xiaowen Wu et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(5):1082-1095. DOI:10.1109/TVLSI.2013.2263397 2014
Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays [0.03%]
Sanyal, Alodeep; Ganeshpure, Kunal; Kundu et al. Sanyal et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2012;20(3):424-436. DOI:10.1109/TVLSI.2011.2106169 2012
Delay Test for Diagnosis of Power Switches [0.03%]
Khursheed, Saqib; Shi, Kan; Al-Hashimi et al. Khursheed et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(2):197-206. DOI:10.1109/TVLSI.2013.2239319 2014
Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing [0.03%]
Saeed, Samah Mohamed; Sinanoglu, Ozgur Saeed
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(3):516-521. DOI:10.1109/TVLSI.2013.2248764 2014