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期刊名：Ieee transactions on very large scale integration (vlsi) systems

缩写：IEEE T VLSI SYST

ISSN：1063-8210

e-ISSN：1557-9999

IF/分区：3.2/Q2

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共收录本刊相关文章索引1430条
Clinical Trial Case Reports Meta-Analysis RCT Review Systematic Review
Classical Article Case Reports Clinical Study Clinical Trial Clinical Trial Protocol Comment Comparative Study Editorial Guideline Letter Meta-Analysis Multicenter Study Observational Study Randomized Controlled Trial Review Systematic Review
Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of ${\rm GF}(2^{m})$ [0.03%] 适用于特殊类〈formula formulatype=\"inline\"〉〈tex Notation=\"TeX\"〉${\\rm GF}(2^{m})$〈/tex〉的低复杂度数字串行脉动蒙哥马利乘法器
Talapatra, Somsubhra; Rahaman, Hafizur; Mathew et al. Talapatra et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010;18(5):847-852. DOI:10.1109/TVLSI.2009.2016753 2010
Resistive Threshold Logic [0.03%] 电阻阈值逻辑
James, Alex Pappachen; Francis, Linu Rose V. J.; Kumar et al. James et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(1):190-195. DOI:10.1109/tvlsi.2012.2232946 2014
Finite field inversion over the dual basis [0.03%] 基于对偶基的有限域逆运算
Fenn, S.T.J.; Benaissa, M.; Taylor et al. Fenn et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1996;4(1):134-137. DOI:10.1109/92.486087 1996
Design of low-error fixed-width modified booth multiplier [0.03%] 低误差固定宽度改进Booth乘法器的设计
Kyung-Ju Cho, ; Kwang-Chul Lee, ; Jin-Gyun Chung et al. Kyung-Ju Cho et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2004;12(5):522-531. DOI:10.1109/TVLSI.2004.825853 2004
Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks [0.03%] 通过在逻辑块之间共享透明扫描序列进行测试压缩
Pomeranz, Irith Pomeranz
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(4):792-802. DOI:10.1109/TVLSI.2013.2256438 2014
Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications [0.03%] 面向带宽的实时移动视频应用中运动估计的算法与架构设计
Hsieh, Jui-Hung; Chang, Tian-Sheuan Hsieh
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013;21(1):33-42. DOI:10.1109/TVLSI.2011.2178439 2013
Jitter of Delay-Locked Loops Due to PFD [0.03%] 由于PFD引起的延迟锁定环抖动
Gholami, Mohammad; Ardeshir, Gholamreza Gholami
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(10):2176-2180. DOI:10.1109/TVLSI.2013.2284501 2014
Multivoltage Aware Resistive Open Fault Model [0.03%] 多电压感知电阻开路故障模型
Mohammadat, Mohamed Tagelsir; Ali, Noohul Basheer Zain; Hussin et al. Mohammadat et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(2):220-231. DOI:10.1109/TVLSI.2013.2243926 2014
An Ultralow Power Multirate FSK Demodulator With Digital-Assisted Calibrated Delay-Line Based Phase Shifter for High-Speed Biomedical Zero-IF Receivers [0.03%] 一种超低功耗多速率FSK解调器，采用数字辅助校准延迟线式移相器，适用于高速生物医学零中频接收机。
Shih, Horng-Yuan; Chen, Chun-Fan; Chang et al. Shih et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2015;23(1):98-106. DOI:10.1109/TVLSI.2013.2297834 2015
Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique [0.03%] 采用传输门逻辑电路技术的低电压、低功耗二分频/三分频计数器设计
Yin-Tsung Hwang; Jin-Fa Lin Yin-Tsung Hwang; Jin-Fa Lin
Ieee transactions on very large scale integration (vlsi) systems. 2012;20(9):0-. DOI:10.1109/tvlsi.2011.2161598 2012