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Ieee transactions on very large scale integration (vlsi) systems. 2012;20(9):0-. doi: 10.1109/tvlsi.2011.2161598 Q23.22025

Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique

采用传输门逻辑电路技术的低电压、低功耗二分频/三分频计数器设计

Yin-Tsung Hwang; Jin-Fa Lin

DOI: 10.1109/tvlsi.2011.2161598

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期刊名:Ieee transactions on very large scale integration (vlsi) systems

缩写:IEEE T VLSI SYST

ISSN:1063-8210

e-ISSN:1557-9999

IF/分区:3.2/Q2

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Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique