P R Shrestha,D M Nminibapiel,D Veksler et al.
P R Shrestha et al.
The inevitable current overshoot which follows forming in filamentary RRAM devices is often perceived as a source of variability that should be minimized. This sentiment has led to efforts to curtail the overshoot by decreasing the parasiti...
Subband engineering in n-type silicon nanowires using strain and confinement [0.03%]
应变和限制下的n型硅纳米线的子带工程学研究
Zlatan Stanojević,Viktor Sverdlov,Oskar Baumgartner et al.
Zlatan Stanojević et al.
We present a model based on k · p theory which is able to capture the subband structure effects present in ultra-thin strained silicon nanowires. For electrons, the effective mass and valley minima are calculated for different crystal orie...
Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks [0.03%]
氧化和还原退火对Ge/La2O3/ZrO2栅极堆叠的电学性能影响研究
Christoph Henkel,Per-Erik Hellström,Mikael Ostling et al.
Christoph Henkel et al.
The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gat...
PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process [0.03%]
一种基于180nmCMOS工艺的高速PNP光电双极型晶体管传感器
P Kostov,W Gaberl,M Hofbauer et al.
P Kostov et al.
This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180 nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low...
Johann Cervenka,Hans Kosina,Siegfried Selberherr et al.
Johann Cervenka et al.
The potential of strained DOTFET technology is demonstrated. This technology uses a SiGe island as a stressor for a Si capping layer, into which the transistor channel is integrated. The structure information of fabricated samples is extrac...
Joo C Chan,Hoang Tran,James W Pattison et al.
Joo C Chan et al.
One-dimensional nanostructures such as silicon nanowires (SiNW) are attractive candidates for low power density electronic and optoelectronic devices including sensors. A new simple method for SiNW bulk synthesis[1, 2] is demonstrated in th...
Small-Signal Performance and Modeling of sub-50nm nMOSFETs with f above 460-GHz [0.03%]
亚50纳米、fT超过460吉赫的nMOSFET的小信号性能和建模方法研究
V Dimitrov,J Heng,K Timp et al.
V Dimitrov et al.
We have fabricated and tested the performance of sub-50nm gate nMOSFETs to assess their suitability for mixed signal applications in the super high frequency (SHF) band, i.e. 3-30GHz. For a 30nm×40 μm×2 device, we found f(T) =465GHz at V...
Seth J Wilk,Asha Balijepalli,Joseph Ervin et al.
Seth J Wilk et al.
CMOS compatible, high voltage SOI MESFETs have been fabricated using a standard 3.3V CMOS process without any changes to the process flow. A 0.6μm gate length device operates with a cut-off frequency of 7.3GHz and a maximum oscillation fre...