Ieee transactions on very large scale integration (vlsi) systems文章索引

期刊名：Ieee transactions on very large scale integration (vlsi) systems

缩写：IEEE T VLSI SYST

ISSN：1063-8210

e-ISSN：1557-9999

IF/分区：3.2/Q2

共收录本刊相关文章索引1430条

Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style [0.03%]

Goel, S.; Kumar, A.; Bayoumi et al. Goel et al.

Ieee transactions on very large scale integration (vlsi) systems. 2006;14(12):1309-1321. DOI:10.1109/tvlsi.2006.887807 2006

Sampling phase detector using a resonant tunneling high electron mobility transistor for microwave phase-locked oscillators [0.03%]

Okazaki, H.; Nakagawa, T.; Muraguchi et al. Okazaki et al.

Ieee transactions on very large scale integration (vlsi) systems. 1998;6(1):39-42. DOI:10.1109/92.661243 1998

A combined gate replacement and input vector control approach for leakage current reduction [0.03%]

Lin Yuan; Gang Qu Lin Yuan; Gang Qu

Ieee transactions on very large scale integration (vlsi) systems. 2006;14(2):173-182. DOI:10.1109/tvlsi.2005.863747 2006

Leakage Minimization of SRAM Cells in a Dual- and Dual- Technology [0.03%]

Amelifard, B.; Fallah, F.; Pedram et al. Amelifard et al.

Ieee transactions on very large scale integration (vlsi) systems. 2008;16(7):851-860. DOI:10.1109/tvlsi.2008.2000459 2008

Gate oxide leakage current analysis and reduction for VLSI circuits [0.03%]

Dongwoo Lee; Blaauw, D.; Sylvester, D. Dongwoo Lee; Blaauw

Ieee transactions on very large scale integration (vlsi) systems. 2004;12(2):155-166. DOI:10.1109/tvlsi.2003.821553 2004

A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems [0.03%]

Kyung Ki Kim; Yong-Bin Kim Kyung Ki Kim; Yong-Bin Kim

Ieee transactions on very large scale integration (vlsi) systems. 2009;17(4):517-528. DOI:10.1109/tvlsi.2008.2007958 2009

Distributed sleep transistor network for power reduction [0.03%]

Changbo Long; Lei He Changbo Long; Lei He

Ieee transactions on very large scale integration (vlsi) systems. 2004;12(9):937-946. DOI:10.1109/tvlsi.2004.832939 2004

Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing [0.03%]

De-Shiuan Chiou; Shih-Hsin Chen; Shih-Chieh Chang De-Shiuan Chiou; Shih-Hsin Chen; Shih-Chieh Chang

Ieee transactions on very large scale integration (vlsi) systems. 2009;17(9):1330-1334. DOI:10.1109/tvlsi.2008.2001247 2009

Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm [0.03%]

Yu-Chi Tsao; Ken Choi Yu-Chi Tsao; Ken Choi

Ieee transactions on very large scale integration (vlsi) systems. 2012;20(2):366-371. DOI:10.1109/tvlsi.2010.2095892 2012

Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip [0.03%]

Pham, Phi-Hung; Song, Junyoung; Park et al. Pham et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013;21(1):173-177. DOI:10.1109/tvlsi.2011.2181545 2013