Ieee transactions on very large scale integration (vlsi) systems文章索引

期刊名：Ieee transactions on very large scale integration (vlsi) systems

缩写：IEEE T VLSI SYST

ISSN：1063-8210

e-ISSN：1557-9999

IF/分区：3.2/Q2

共收录本刊相关文章索引1430条

Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit [0.03%] 协作定时恢复电路中二进制相位检测器的线性化技术

Yoo, Byoung-Joo; Bae, Woo-Rham; Han et al. Yoo et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(6):1226-1237. DOI:10.1109/TVLSI.2013.2269616 2014

Low-Complexity Hardware Design for Fast Solving LSPs With Coordinated Polynomial Solution [0.03%] 基于协同多项式解法的低复杂度硬件设计，用于快速求解LSPs

Chang, Chung-Hsien; Chen, Bo-Wei; Chen et al. Chang et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2015;23(2):230-243. DOI:10.1109/TVLSI.2014.2305699 2015

Scalable Multilevel Vectorless Power Grid Voltage Integrity Verification [0.03%] 可扩展的多级无矢量电力网格电压完整性验证

Feng, Zhuo Feng

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013;21(8):1388-1397. DOI:10.1109/TVLSI.2012.2212033 2013

Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating [0.03%] 数据驱动时钟门控中触发器分组的设计流程

Wimer, Shmuel; Koren, Israel Wimer

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(4):771-778. DOI:10.1109/TVLSI.2013.2253338 2014

Systematic IEEE rounding method for high-speed floating-point multipliers [0.03%] 用于高速浮点乘法器的系统化IEEE舍入方法

Quach, N.T.; Takagi, N.; Flynn et al. Quach et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2004;12(5):511-521. DOI:10.1109/TVLSI.2004.825860 2004

Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture [0.03%] 面向低功耗粗粒度可重构架构的动态上下文压缩

Kim, Yoonjin; Mahapatra, Rabi N. Kim

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010;18(1):15-28. DOI:10.1109/TVLSI.2008.2006846 2010

Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems [0.03%] 面向节能实时系统的SEU容错的联合时间和信息冗余方法

Ejlali, A.; Al-Hashimi, B.M.; Schmitz et al. Ejlali et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2006;14(4):323-335. DOI:10.1109/TVLSI.2006.874355 2006

Decoding the Golden Code: A VLSI Design [0.03%] 解码黄金代码：一种VLSI设计

Cerato, B.; Masera, G.; Viterbo et al. Cerato et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2009;17(1):156-160. DOI:10.1109/TVLSI.2008.2003163 2009

A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes [0.03%] 一类由正交拉丁方码导出的SEC-DED-DAEC码

Reviriego, Pedro; Pontarelli, Salvatore; Evans et al. Reviriego et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2015;23(5):968-972. DOI:10.1109/TVLSI.2014.2319291 2015

FTQLS: Fault-Tolerant Quantum Logic Synthesis [0.03%] FTQLS：容错量子逻辑综合

Lin, Chia-Chun; Chakrabarti, Amlan; Jha et al. Lin et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(6):1350-1363. DOI:10.1109/TVLSI.2013.2269869 2014