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期刊名：Ieee transactions on very large scale integration (vlsi) systems

缩写：IEEE T VLSI SYST

ISSN：1063-8210

e-ISSN：1557-9999

IF/分区：3.2/Q2

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共收录本刊相关文章索引1430条
Clinical Trial Case Reports Meta-Analysis RCT Review Systematic Review
Classical Article Case Reports Clinical Study Clinical Trial Clinical Trial Protocol Comment Comparative Study Editorial Guideline Letter Meta-Analysis Multicenter Study Observational Study Randomized Controlled Trial Review Systematic Review
Formal Verification of Architectural Power Intent [0.03%] 架构功耗意图的形式化验证
Hazra, Aritra; Goyal, Sahil; Dasgupta et al. Hazra et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013;21(1):78-91. DOI:10.1109/tvlsi.2011.2180548 2013
Leakage power analysis and reduction during behavioral synthesis [0.03%] 行为综合过程中的功耗泄漏分析与降低
Khouri, K.S.; Jha, N.K. Khouri
Ieee transactions on very large scale integration (vlsi) systems. 2002;10(6):876-885. DOI:10.1109/tvlsi.2002.808436 2002
An Analytical Latency Model for Networks-on-Chip [0.03%] 片上网络的分析性延迟模型
Kiasari, Abbas Eslami; Lu, Zhonghai; Jantsch et al. Kiasari et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013;21(1):113-123. DOI:10.1109/tvlsi.2011.2178620 2013
Table of contents [0.03%] 目录
Ieee transactions on very large scale integration (vlsi) systems. 2012;20(9):-. DOI:10.1109/tvlsi.2012.2197685 2012
A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations [0.03%] 一种用于近似、高效对数与反对数计算的快速硬件方法
Paul, S.; Jayakumar, N.; Khatri et al. Paul et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2009;17(2):269-277. DOI:10.1109/TVLSI.2008.2003481 2009
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture [0.03%] 采用异构双处理单元架构的高效抗功耗分析双域椭圆曲线密码处理器
Lee, Jen-Wei; Chung, Szu-Chi; Chang et al. Lee et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(1):49-61. DOI:10.1109/TVLSI.2013.2237930 2014
Power estimation in adiabatic circuits: a simple and accurate model [0.03%] 绝热电路中的功耗估算：一种简单而精确的模型
Alioto, M.; Palumbo, G. Alioto
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2001;9(5):608-615. DOI:10.1109/92.953495 2001
Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code [0.03%] 利用十进制矩阵码提高对多重单元翻转的内存可靠性
Guo, Jing; Xiao, Liyi; Mao et al. Guo et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(1):127-135. DOI:10.1109/TVLSI.2013.2238565 2014
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic [0.03%] 具有自适应保持逻辑的面向老龄化的可靠乘法器设计
Lin, Ing-Chao; Cho, Yu-Hung; Yang et al. Lin et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2015;23(3):544-556. DOI:10.1109/TVLSI.2014.2311300 2015
Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function [0.03%] 具有双曲正切激活函数的神经网络的高效VLSI实现
Zamanlooy, Babak; Mirhassani, Mitra Zamanlooy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(1):39-48. DOI:10.1109/TVLSI.2012.2232321 2014