Ieee transactions on very large scale integration (vlsi) systems文章索引

期刊名：Ieee transactions on very large scale integration (vlsi) systems

缩写：IEEE T VLSI SYST

ISSN：1063-8210

e-ISSN：1557-9999

IF/分区：3.2/Q2

共收录本刊相关文章索引1430条

Cell-Based Process Resilient Multiphase Clock Generation [0.03%] 基于细胞的工艺鲁棒多相时钟生成

Ding, Ruo-Ting; Huang, Shi-Yu; Tzeng et al. Ding et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013;21(12):2348-2352. DOI:10.1109/TVLSI.2012.2230347 2013

A tree-matching chip [0.03%] 一棵匹配芯片

Krishna, V.; Ranganathan, N.; Ejnioui et al. Krishna et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1999;7(2):277-280. DOI:10.1109/92.766755 1999

Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master–Slave Flip-Flops [0.03%] 重新审视基于传输门的主从触发器的高速设计准则

Consoli, Elio; Palumbo, Gaetano; Pennisi et al. Consoli et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2012;20(2):284-295. DOI:10.1109/TVLSI.2010.2098426 2012

A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic [0.03%] 一种新型混合并行前缀加法器架构，具有高效的时序-面积特性

Das, S.; Khatri, S.P. Das

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2008;16(3):326-331. DOI:10.1109/TVLSI.2007.915507 2008

Low-Power, Minimally Invasive Process Compensation Technique for Sub-Micron CMOS Amplifiers [0.03%] 用于亚微米CMOS放大器的低功耗、微创工艺补偿技术

Mukadam, Mustansir Y.; Gouveia-Filho, Oscar C.; Kramer et al. Mukadam et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(1):1-12. DOI:10.1109/TVLSI.2012.2232685 2014

The Chimaera reconfigurable functional unit [0.03%] 奇美拉可重构功能单元

Hauck, S.; Fry, T.W.; Hosler et al. Hauck et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2004;12(2):206-217. DOI:10.1109/TVLSI.2003.821545 2004

A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection [0.03%] 一种用于基于AdaBoost的实时目标检测的灵活并行硬件架构

Kyrkou, Christos; Theocharides, Theocharis Kyrkou

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2011;19(6):1034-1047. DOI:10.1109/TVLSI.2010.2048224 2011

LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors [0.03%] LP-NUCA：面向高性能低功耗嵌入式处理器的缓存内网络

Gracia, D. S.; Dimitrakopoulos, G.; Arnal et al. Gracia et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2012;20(8):1510-1523. DOI:10.1109/TVLSI.2011.2158249 2012

High-Speed Low-Power Viterbi Decoder Design for TCM Decoders [0.03%] 用于TCM解码器的高速低功耗维特比解码器设计

He, Jinjin; Liu, Huaping; Wang et al. He et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2012;20(4):755-759. DOI:10.1109/TVLSI.2011.2111392 2012

Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator [0.03%] 低电压低功耗双尾比较器的分析与设计

Babayan-Mashhadi, Samaneh; Lotfi, Reza Babayan-Mashhadi

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(2):343-352. DOI:10.1109/TVLSI.2013.2241799 2014