IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2008;16(3):326-331. doi: 10.1109/TVLSI.2007.915507 Q23.22025

A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic

一种新型混合并行前缀加法器架构，具有高效的时序-面积特性

DOI: 10.1109/TVLSI.2007.915507

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