Ieee transactions on very large scale integration (vlsi) systems文章索引

期刊名：Ieee transactions on very large scale integration (vlsi) systems

缩写：IEEE T VLSI SYST

ISSN：1063-8210

e-ISSN：1557-9999

IF/分区：3.2/Q2

共收录本刊相关文章索引1430条

Signal processing at 250 MHz using high-performance FPGA's [0.03%]

Von Herzen, B. Von Herzen

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1998;6(2):238-246. DOI:10.1109/92.678878 1998

Elixir: High-Throughput Cost-Effective Dual-Field Processors and the Design Framework for Elliptic Curve Cryptography [0.03%]

Jyu-Yuan Lai, ; Chih-Tsun Huang, Jyu-Yuan Lai

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2008;16(11):1567-1580. DOI:10.1109/TVLSI.2008.2001239 2008

Customizable elliptic curve cryptosystems [0.03%]

Cheung, R.C.C.; Telle, N.J.; Luk et al. Cheung et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2005;13(9):1048-1059. DOI:10.1109/TVLSI.2005.857179 2005

Design of flexible GF(2/sup m/) elliptic curve cryptography processors [0.03%]

Benaissa, M.; Wei Ming Lim, Benaissa

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2006;14(6):659-662. DOI:10.1109/TVLSI.2006.878235 2006

Cosimulation-based power estimation for system-on-chip design [0.03%]

Lajolo, M.; Raghunathan, A.; Dey et al. Lajolo et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2002;10(3):253-266. DOI:10.1109/TVLSI.2002.1043328 2002

Equalization-Based Digital Background Calibration Technique for Pipelined ADCs [0.03%]

Zeinali, Behzad; Moosazadeh, Tohid; Yavari et al. Zeinali et al.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(2):322-333. DOI:10.1109/TVLSI.2013.2242208 2014

Exact moment matching model of transmission lines and application to interconnect delay estimation [0.03%]

Qingjian Yu, ; Kuh, E.S. Qingjian Yu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1995;3(2):311-322. DOI:10.1109/92.386230 1995

A 3–5 GHz Current-Reuse -Boosted CG LNA for Ultrawideband in 130 nm CMOS [0.03%]

Khurram, M.; Hasan, S.M.R. Khurram

Ieee transactions on very large scale integration (vlsi) systems. 2012;20(3):400-409. DOI:10.1109/tvlsi.2011.2106229 2012

A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm [0.03%]

Sang-Hyun Cho; Chang-Kyo Lee; Sang-Gug Lee; Seung-Tak Ryu Sang-Hyun Cho; Chang-Kyo Lee; Sang-Gug Lee; Seung-Tak Ryu

Ieee transactions on very large scale integration (vlsi) systems. 2012;20(4):765-769. DOI:10.1109/tvlsi.2011.2109743 2012

VLSI architectures for discrete wavelet transforms [0.03%]

Parhi, K.K.; Nishitani, T. Parhi

Ieee transactions on very large scale integration (vlsi) systems. 1993;1(2):191-202. DOI:10.1109/92.238416 1993