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期刊名：Ieee transactions on very large scale integration (vlsi) systems

缩写：IEEE T VLSI SYST

ISSN：1063-8210

e-ISSN：1557-9999

IF/分区：3.2/Q2

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共收录本刊相关文章索引1430条
Clinical Trial Case Reports Meta-Analysis RCT Review Systematic Review
Classical Article Case Reports Clinical Study Clinical Trial Clinical Trial Protocol Comment Comparative Study Editorial Guideline Letter Meta-Analysis Multicenter Study Observational Study Randomized Controlled Trial Review Systematic Review
ADDLL for Clock-Deskew Buffer in High-Performance SoCs [0.03%]
Park, Jung-Hyun; Jung, Dong-Hoon; Ryu et al. Park et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013;21(7):1368-1373. DOI:10.1109/TVLSI.2012.2210742 2013
MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems [0.03%]
Yang, Kai-Jiun; Tsai, Shang-Ho; Chuang et al. Yang et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013;21(4):720-731. DOI:10.1109/TVLSI.2012.2194315 2013
Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation [0.03%]
Chen, T.; Naffziger, S. Chen
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2003;11(5):888-899. DOI:10.1109/TVLSI.2003.817120 2003
Comparison of high-performance VLSI adders in the energy-delay space [0.03%]
Oklobdzija, V.G.; Zeydel, B.R.; Dao et al. Oklobdzija et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2005;13(6):754-758. DOI:10.1109/TVLSI.2005.848819 2005
High-throughput LDPC decoders [0.03%]
Mansour, M.M.; Shanbhag, N.R. Mansour
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2003;11(6):976-996. DOI:10.1109/TVLSI.2003.817545 2003
Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs [0.03%]
Coskun, A.K.; Rosing, T.T.; Whisnant et al. Coskun et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2008;16(9):1127-1140. DOI:10.1109/TVLSI.2008.2000726 2008
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation [0.03%]
Todri, Aida; Bosio, Alberto; Dilillo et al. Todri et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013;21(5):958-970. DOI:10.1109/TVLSI.2012.2197427 2013
Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPs [0.03%]
Kim, Hyunhee; Ahn, Jung Ho; Kim et al. Kim et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013;21(10):1863-1877. DOI:10.1109/TVLSI.2012.2220791 2013
Quantitative analysis and optimization techniques for on-chip cache leakage power [0.03%]
Nam Sung Kim, ; Blaauw, D.; Mudge et al. Nam Sung Kim et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2005;13(10):1147-1156. DOI:10.1109/TVLSI.2005.859476 2005
A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects [0.03%]
Dave, Marshnil; Jain, Mahavir; Shojaei Baghini et al. Dave et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013;21(2):342-353. DOI:10.1109/TVLSI.2012.2185835 2013