首页 文献索引 SCI期刊 AI助手
期刊目录筛选

期刊名：Ieee transactions on very large scale integration (vlsi) systems

缩写：IEEE T VLSI SYST

ISSN：1063-8210

e-ISSN：1557-9999

IF/分区：3.2/Q2

文章目录 更多期刊信息

共收录本刊相关文章索引1430条
Clinical Trial Case Reports Meta-Analysis RCT Review Systematic Review
Classical Article Case Reports Clinical Study Clinical Trial Clinical Trial Protocol Comment Comparative Study Editorial Guideline Letter Meta-Analysis Multicenter Study Observational Study Randomized Controlled Trial Review Systematic Review
CMOS Charge Pump With No Reversion Loss and Enhanced Drivability [0.03%] 无可逆损耗和增强可驱动性的CMOS电荷泵
Kim, Joung-Yeal; Park, Su-Jin; Kwon et al. Kim et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(6):1441-1445. DOI:10.1109/TVLSI.2013.2267214 2014
Economizing TSV Resources in 3-D Network-on-Chip Design [0.03%] 在三维片上网络设计中节约TSV资源
Wang, Ying; Han, Yin-He; Zhang et al. Wang et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2015;23(3):493-506. DOI:10.1109/TVLSI.2014.2311835 2015
PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies [0.03%] Sub-65-nm CMOS技术中的纯PMOS睡眠开关双阈值电压多米诺逻辑
Zhiyu Liu, ; Kursun, V. Zhiyu Liu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2007;15(12):1311-1319. DOI:10.1109/tvlsi.2007.903947 2007
An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS [0.03%] 110 nm CMOS中11.5 Gb/s 1/4波特率CTLE和具有增强高频增益的双抽头DFE
Kim, Yong-Hun; Kim, Young-Ju; Lee et al. Kim et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2015;23(3):588-592. DOI:10.1109/TVLSI.2014.2314147 2015
A Configurable Monitoring Infrastructure for NoC-Based Architectures [0.03%] 基于NoC架构的可配置监控基础架构
Fiorin, Leandro; Palermo, Gianluca; Silvano et al. Fiorin et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(11):2436-2440. DOI:10.1109/TVLSI.2013.2290102 2014
On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard [0.03%] 符合完整IEEE-754标准的便携式宏单元浮点运算器生成器，用于实现除法和开方运算符
Aberbour, M.; Houelle, A.; Mehrez et al. Aberbour et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1998;6(1):114-121. DOI:10.1109/92.661253 1998
Memory power models for multilevel power estimation and optimization [0.03%] 用于多级功耗估算与优化的存储器功率模型
Schmidt, E.; von Colln, G.; Kruse et al. Schmidt et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2002;10(2):106-109. DOI:10.1109/92.994987 2002
A structure-oriented power modeling technique for macrocells [0.03%] 面向结构的宏单元功率建模技术
Jiing-Yuan Lin, ; Wen-Zen Shen, ; Jing-Yang Jou et al. Jiing-Yuan Lin et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1999;7(3):380-391. DOI:10.1109/92.784099 1999
Unified VLSI systolic array design for LZ data compression [0.03%] 用于LZ数据压缩的统一VLSI阵列设计
Shih-Arn Hwang, ; Cheng-Wen Wu, Shih-Arn Hwang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2001;9(4):489-499. DOI:10.1109/92.931226 2001
Grammar-based hardware synthesis from port-size independent specifications [0.03%] 基于语法的硬件综合，适用于端口尺寸无关的规范
Oberg, J.; Kumar, A.; Hemani et al. Oberg et al.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2000;8(2):184-194. DOI:10.1109/92.831438 2000