A transient-improved low-dropout regulator with nested flipped voltage follower structure [0.03%]
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Hua Chen; Ka Nang Leung
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György Csaba; Markus Becherer; Wolfgang Porod
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A new digital control method for a voltage source inverter to compensate for imbalance of output voltage [0.03%]
一种新的电压源逆变器数字控制方法，用于补偿输出电压的不平衡
Jian-Min Wang; Po-Jung Tseng; Shang-Chin Yen; Pang-Jung Liu; Huang-Jen Chiu
Jian-Min Wang; Po-Jung Tseng; Shang-Chin Yen; Pang-Jung Liu; Huang-Jen Chiu
Ju-Hong Lee; Yi-Lin Shieh
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Introduction [0.03%]
介绍
Arpad I. Csurgay; Wolfgang Porod; Stephen M. Goodnick
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Analysis and design of a two-transformer active-clamping ZVS isolated inverse-SEPIC converter [0.03%]
双变压器有源箝位ZVS隔离逆SEPIC变换器的分析与设计
Yu-Kang Lo; Jing-Yuan Lin; Shang-Chin Yen; Liang-Chun Lin
Yu-Kang Lo; Jing-Yuan Lin; Shang-Chin Yen; Liang-Chun Lin
Why- and how- to integrate Verilog-A compact models in SPICE simulators [0.03%]
为什么以及如何将Verilog-A紧凑型模型集成到SPICE模拟器中
Maria-Anna Chalkiadaki; Cédric Valla; Frédéric Poullet; Matthias Bucher
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George Raikos; Spyridon Vlassis
George Raikos; Spyridon Vlassis
Huang-Jen Chiu; Yu-Kang Lo; Yu-Chen Chang; Po-Jung Tseng; Yu-Chen Liu
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Design and implementation of a digitally controlled single-inductor dual-output (SIDO) buck converter [0.03%]
数控单电感双输出降压变换器的设计与实现
Chien-Hung Tsai; Chun-Hung Yang; Chi-Wai Leng
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