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IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1999;7(3):345-358. doi: 10.1109/92.784096 Q23.22025

Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms

面向全搜索块匹配算法的高性价比VLSI架构与缓冲区大小优化

Yuan-Hau Yeh, ; Chen-Yi Lee,

DOI: 10.1109/92.784096

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Copyright © IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 中文内容为AI机器翻译,仅供参考!

期刊名:Ieee transactions on very large scale integration (vlsi) systems

缩写:IEEE T VLSI SYST

ISSN:1063-8210

e-ISSN:1557-9999

IF/分区:3.2/Q2

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Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms