$\Delta\Sigma$ ADC 阻塞器容限的设计技术" />
首页 正文

IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2015;23(1):54-67. doi: 10.1109/TVLSI.2014.2303815 Q23.22025

Design Techniques to Improve Blocker Tolerance of Continuous-Time $\Delta\Sigma$ ADCs

提高连续时间 $\Delta\Sigma$ ADC 阻塞器容限的设计技术

Geddada, Hemasundar Mohan; Park, Chang-Joon; Jeon, Hyung-Joon; Silva-Martinez, Jose; Karsilayan, Aydin Ilker; Garrity, Douglas

DOI: 10.1109/TVLSI.2014.2303815

摘要 查看摘要

Copyright © IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 中文内容为AI机器翻译,仅供参考!

期刊名:Ieee transactions on very large scale integration (vlsi) systems

缩写:IEEE T VLSI SYST

ISSN:1063-8210

e-ISSN:1557-9999

IF/分区:3.2/Q2

文章目录 更多期刊信息

全文链接
引文链接
复制
已复制!
推荐内容
Design Techniques to Improve Blocker Tolerance of Continuous-Time $\Delta\Sigma$ ADCs