IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2005;13(2):201-210. doi: 10.1109/TVLSI.2004.840776 Q23.22025

A "Flying-Adder" frequency synthesis architecture of reducing VCO stages

一种减少压控振荡器级数的“飞蛇”频率合成架构

DOI: 10.1109/TVLSI.2004.840776

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