IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(5):983-994. doi: 10.1109/TVLSI.2013.2263155 Q23.22025
On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time
一种粗粒度可重构架构中的片上存储器层次结构，用于压缩存储空间并减少重构时间和数据访问时间。
DOI: 10.1109/TVLSI.2013.2263155
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期刊名：Ieee transactions on very large scale integration (vlsi) systems
缩写：IEEE T VLSI SYST
ISSN：1063-8210
e-ISSN：1557-9999
IF/分区：3.2/Q2
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On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time