IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(5):1197-1201. doi: 10.1109/TVLSI.2013.2265278 Q23.22025

LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology

DOI: 10.1109/TVLSI.2013.2265278

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