IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2005;13(7):872-877. doi: 10.1109/TVLSI.2005.850125 Q23.22025

High-speed architectures for parallel long BCH encoders

并行长BCH编码器的高速架构

DOI: 10.1109/TVLSI.2005.850125

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