IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1998;6(4):634-642. doi: 10.1109/92.736137 Q23.22025

On circuit clustering for area/delay tradeoff under capacity and pin constraints

基于容量与引脚约束下用于面积/延迟权衡的电路聚类方法

DOI: 10.1109/92.736137

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