IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2002;10(4):416-422. doi: 10.1109/TVLSI.2002.807764 Q23.22025

System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip

面向参数化片上系统中帕累托最优配置的系统级探索

DOI: 10.1109/TVLSI.2002.807764

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