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IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014;22(3):631-640. doi: 10.1109/TVLSI.2013.2251430 Q23.22025

Mapping Loop Structures Onto Parametrized Hardware Pipelines

Le Masle, Adrien; Luk, Wayne

DOI: 10.1109/TVLSI.2013.2251430

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Copyright © IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 中文内容为AI机器翻译,仅供参考!

期刊名:Ieee transactions on very large scale integration (vlsi) systems

缩写:IEEE T VLSI SYST

ISSN:1063-8210

e-ISSN:1557-9999

IF/分区:3.2/Q2

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Mapping Loop Structures Onto Parametrized Hardware Pipelines