IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013;21(9):1756-1761. doi: 10.1109/tvlsi.2012.2218839 Q23.22025

Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes

DOI: 10.1109/tvlsi.2012.2218839

摘要

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