International Journal of Circuit Theory and Applications. 1997;25(5):319-334. doi: 10.1002/(sici)1097-007x(199709/10)25:5<319::aid-cta976>3.0.co;2-u Q31.62025
Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology
DOI: 10.1002/(sici)1097-007x(199709/10)25:5<319::aid-cta976>3.0.co;2-u
摘要

期刊名:International journal of circuit theory and applications
缩写:INT J CIRC THEOR APP
ISSN:0098-9886
e-ISSN:1097-007X
IF/分区:1.6/Q3
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Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology